CPU Architecture Engineer - Singapore

关于这个机会

The Server Silicon Design and Application Team drives cutting-edge innovation by designing, developing, and producing CPUs for data center servers. With a combination of engineers, researchers, and specialists, the team focuses on creating chips that are high-performance, energy-efficient, and highly reliable, powering a wide range of electronic devices and systems. Responsibilities: - Based on product requirements, participate in SoC system architecture design and build SoC analysis and evaluation frameworks; - Design and optimize SoC chip architecture according to system performance, power, and cost requirements; responsible for IP selection, as well as the formulation and design of RAS, DFX, subsystem, and low-power solutions; - Analyze system performance bottlenecks for typical application scenarios and benchmarks, and propose improvement solutions; - Collaborate with chip design and verification teams to conduct SoC performance testing and optimization; - Drive key technology breakthroughs; work with upstream and downstream teams on solution research, feasibility studies, and exploration of algorithms and hardware architectures; - Continuously track industry technology trends and identify valuable core technology points and technical directions; - Participate in system-level STCO (System Technology Co-Optimization), planning chip solutions and technology roadmaps from packaging and system-level perspectives.

任职要求

Minimum Qualification(s): - Bachelor's degree or above in Microelectronics, Integrated Circuits, Electronic Engineering, or a related field; Master's or PhD preferred; - 5+ years of SoC R&D experience; - Familiar with CPU architecture, with in-depth knowledge of OS, system software, and chip architecture and design; - Forward-thinking mindset with the ability to drive product innovation; - Capable of independently conducting chip PPA (Power, Performance, Area) analysis; - Experience in server SoC architecture; - Knowledge of advanced process nodes and advanced packaging technologies (2.5D, 3D, CoWoS, EMIB), as well as system-level packaging (wafer-scale, SOIC).

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